Memory Layout Designer

Role: Looking for Memory Layout Designer

 

Skills/ Experience:

 

·         Candidate must have experience in layout design of memory leaf cells and at top level of memories.

·         Candidate should have good communication skills (verbal & oral).

·         Candidate should have worked on 65nm / 45nm / 28nm process technologies and have understanding of issues like WPE, LOD effects.

·         Candidate must have good understanding of physical verification checks DRC, LVS, ERC and reliability checks IR and EM.

·         Candidate must have worked on cadence tools for design and Cadence / Mentor / Synopsys tools for physical verification checks.

·         Candidate must have good understanding of Basics of CMOS circuits.

·         Preferable candidate to have Skill and perl scripting experience to develop layout and schematic tiller.

·         Experience with back-end circuit validation techniques including DRC, LVS, EM, IR, and noise is also a requirement.

·         In addition to having a strong background in custom circuit design, the candidate is also expected to be familiar with scripting languages like TCL, PERL.

 

For further details, please get in touch with Tharuna on tharunaprabhaa@vertxsolutions.net