Must have experience in front end ASIC Design
Must have Bachelors in EE from a reputed university
Must have module level design experience
Must have working knowledge of Verilog, and Modelsim/Questasim, ncsim and/or VCS tools
Must have a clear understanding of digital electronics fundamentals
Must have module level verification experience and code coverage
Must have UNIX platform experience alongwith perl, tcl, shell scripting
Wireless domain (preferably Baseband) knowledge will be a big plus
Exposure to Synthesis, DFT, Timing Simulations, Formal Verification will be a big plus
Understanding of interface protocol like 12C, SPI, UART, AMBA, USB, DMA will be required for Senior position
Please get in touch for more details at sadasivamd@vertxsolutions.net or +91 98400 34160
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